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may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation s o l v e d b y t m features 1a output current 1.4mhz constant frequency operation 97% effciency possible 0.5a (max.) shutdown current adjustable output voltage no external fets or schottky diode required uses small value inductors and ceramic output capacitors low dropout operation: 100% duty cycle soft start and t hermal shutdown protection easy frequency synchonization lead free, rohs compliant package: l small (3mm x 3mm) 10 pin dfn or msop applications mobile phones pdas dscs mp3 players usb devices point of use power the sp6652 is a high effciency, synchronous buck regulator ideal for portable applications using one li-ion cell, with up to 1a of output current. the 1.4mhz switching frequency and pwm control loop are optimized for a small value inductor and ceramic output capacitor, for space constrained portable designs. in addition, the input voltage range of 2.7v to 5.5v; excellent transient response, output accuracy, and ability to transition into 100% duty cycle operation -- further extending useful battery life -- make the sp6652 a superior choice for a wide range of portable power applications. a logic level shutdown control, external clock synchronization, and forced-pwm or automatic control inputs are provided. other features include soft-start, over current protection and 140oc over-temperature shutdown . t ypical a pplication circuit description 1a, high effciency, fixed 1.4 mhz current mode pwm buck regulator v out 3.3v at 1a 10 f 100k ? 340k ? 4.7 h v in 10 f 10nf 4k ? 1 2 3 4 5 10 9 8 7 6 sp6652 p gnd s gnd fb comp sd lx p vin s vin sync mod e enable shutdow n 3.6v - 5.5v 10 ? 1 f sp6652 sp6652 10 pin df n 10 9 8 7 6 1 2 3 4 5 p gnd s gnd fb comp sd lx p vi n s vi n syn c mod e
may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation pv in ,s vin ........................................................................... -0.3v to 6.0v p gnd to s gnd ..................................................................... -0.3v to 0.3v lx to p gnd .............................................................. - 0.3v to p vin +0.3v storage temperature .................................................... -65 c to 150 c operating temperature .................................................. -40c to +85c absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sec - tions of the specifcations below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. e lectrical characteristics v in = uv in = v sdn = 3.6v, i o = 0ma, t amb = -40c to +85c, typical values at 27c unless otherwise noted. the ? denotes the specifcations which apply over the full temperature range, unless otherwise specifed. parameter min typ max units conditions input operating voltage 2.85 5.5 v ? result of i q measurement at v in = p vin = 5.5v fb set voltage 0.784 0.8 0.816 v ? fb set current - 0.0 a ? v fb = 0.8v overall fb accuracy -4 4 % ? fb = comp switching frequency . .4 .6 mhz mode = sd = v in minimum on-time-duration 00 00 ns v fb = 1.0v, v comp = 0.2v sync tracking frequency .0 .0 mhz ? mode = sd = v in , v fb =1.0v sync input current - 0.0 a ? sync logic threshold low 0.3 0.6 v ? high to low transition sync logic threshold high .7 v ? low to high transition pmos switch resistance 0.4 0.6 ? ? i pmos = 200ma nmos switch resistance 0.4 0.6 ? ? i nmos = 200ma inductor current limit 1.3 .5 .7 a ? v fb = 0.4v, mode = sd = v in lx leakage current -3 0. 3 a ? sd = zerov v in quiecent current 5 ma v in = 3.6v, mode = sd = v in 3 0 ma v in = 5.5v, mode = sd = v in uvlo undervoltage lockout threshold, v in falling .55 .7 2.85 v ? sd = v in uvlo hysteresis 6 % soft start current 4 a ? sd = v in , v comp = 1v sd mode input current - 0.0 a ? sd mode input threshold voltage 0.6 0.9 v ? high to low transition .5 1.8 v ? low to high transition slope compensation 700 ma/ s rising over-temperature trip point 40 c over-temperature hysteresis 4 c error amplifer transconductance ma/v
3 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation pin description sp665 2 10 pin msop 10 9 8 7 6 lx p s vi n syn c mod e p gn d s gn d fb comp sd 1 2 3 4 5 vin sp6652 10 pin df n 10 9 8 7 6 1 2 3 4 5 p gnd s gnd fb comp sd lx p vi n s vi n syn c mod e pin number pin name description p gnd power ground pin. synchronous rectifer current returns through this pin. s gnd internal ground pin. control circuitry returns current to this pin. 3 fb external feedback network input connection. connect a resistor from fb to ground and from fb to v out to control the output voltage. regulation point at fb = 0.8v typical. 4 comp compensation pin for error loop. connect an r and c in series to ground to control open loop pole and zero. 5 sd shutdown control input. tie pin to v in for normal operation, tie to ground for shutdown. ttl input threshold. 6 mode connect this pin to v in . 7 sync an external clock signal can be connected to this pin to synchronize the switching frequency. 8 s vin internal supply voltage. control circuitry is powered from from this pin. use an rc flter close to the pin to cut down supply noise. 9 p vin supply voltage for the output driver stage. inductor charging current passes through this pin. 0 lx inductor switching node. inductor tied between this pin and the output capacitor to create regulated output voltage.
4 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation functional d iagram p ark pfm clamp clr r s rst slope compensatio n cntr r s qn q reference noswitch v0p3r vref a=3 gm a 300ma 2ua +v +v internal suppl y str t soft soft str t chg soft start m 7.5m v 7.5m v dchg fb_lo q q bli m refok pre-amp error amp s vin p vin ilpk chg current loop comparator pfm loop comparator 0.75v pwm mode comparator clk charging pmos replic a 0.3 v 0.75v refok v in sd shutdown tr anslator go pfm go pwm mode select pwm/pfm clk go pfm go pwm 0.75v 0.75v pfm node park clamp peak and tr ough current detector r s cl r +v lx 100ma 0ma + - + - - by osc sync co rl vout l rf1 rf2 fb comp mode sync sgnd pgnd sd driver dchg changin g pmos lx pwm/pfm inductor current clam p 0.3 v low v o indicator fb_lo clk clock generator internal gn d ilpk
5 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation current mode control and slope compensation the sp6652 is designed to use low value ceramic capacitors and low value inductors to reduce the converters volume and cost in portable devices. current mode pwm control was, therefore, chosen for the ease of compensation when using ceramic output capacitors and better transient line rejec - tion, which is important in battery powered applications. current mode control spreads the two poles of the output power train flter far apart so that the modulator gain crosses over at -20db/decade instead of the usual -40db/decade. the external compensation network is, simply, a series rc circuit con - nected between ground and the output of the internal transconductance error amplifer. it is well known that an unconditional insta - bility exists for any fxed frequency current- mode converter operating above 50% duty cycle. a simple, constant-slope compensa - tion is chosen to achieve stability under these conditions. the most common high duty cycle application is a li-ion battery powered regulator with a 3.3v output (d 90%). since the current loop is critically damped when the compensation slope (denoted mc v ) equals the negative discharge slope (denoted m2 v ), the amount of slope compensation chosen is, therefore: m2 = di l /dt off =-v out /l = -3.3v/4.7h = -702ma/s m v = m?r pmos mc v = -m v = 702ma/s?0.2? = 140mv/s, for r pmos = 0.20? the inductor current is sensed as a voltage across the pmos charging switch and the nmos synchronous rectifer (see block diagram). during inductor current charge, v(pv in )-v(lx) represents the charging cur - rent ramp times the resistance of the pmos charging switch. to keep the effective current slope compensation constant (remembering current is being compensated, not voltage) the voltage slope must be proportional to r pmos . to account for this, the slope com - pensation voltage is internally generated with a bias current that is also proportional to r pmos . over current protection in steady state closed loop operation the voltage at the comp pin controls the duty cycle. due to the current mode control and the slope compensation, this voltage will be: v( comp )? { i lpk ? r pmos + mc v ? t on + v be (q1) } the comp node will be clamped when its voltage tries to exceed v( blim ) + v be (q1). the v be (q1) term is cancelled by v be (q2) at the output of the translator. the correct value of clamp voltage is, therefore: v( blim ) = i l ( max )? r pmos + mcv ?t on the i l(max) term is generated with a bias current that is proportional to r pmos , to keep the value of current limit approximately constant over process and temperature variations, while the mc v ?t on is generated by a peak-holding circuit that senses the amplitude of the slope compensation ramp at the end of t on . there is minimum on-time ( t on ) generated even if the comp node is at zerov, since the peak current comparator is reset at the end of a charge cycle and is held low during a blanking time after the start of the next charge cycle. this is necessary to swamp the transients in the inductor current ramp around switching times. the minimum t on (100ns, nominally) is not suffcient for the comp node to keep control of the current d etailed description
6 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation when the output voltage is low. the inductor current tends to rise until the energy loss from the discharge resistances are equal to the energy gained during the charge phase. for this reason, the clock frequency is cut in half when the feedback pin is below 0.3v, ef - fectively reducing the minimum duty cycle in half. above v( fb ) = 0.3v the clock frequency is normal (see typical operating character - istics: inductor current vs. v out ) voltage loop and compensation in pwm mode the voltage loop section of the circuit con - sists of the error amplifer and the translator circuits (see functional diagram). the input of the voltage loop is the 0.8v reference volt - age minus the divided down output voltage at the feedback pin. the output of the error amplifer is translated from a ground referred signal (the comp node) to a power input voltage referred signal. the output of the voltage loop is fed to the positive terminal of the current loop comparator, and repre - sents the peak inductor current necessary to close the loop. the total power supply loop is compensated with a series rc network connected from the comp pin to ground. compensation is simple due to current-mode control. the modulator has two dominant poles: one at a low frequency, and one above the crossover frequency of the loop, as seen in the graph below, linearized modulator frequency response vs. inductor value. the low frequency pole for l1= 5h is 4khz, the second pole is 500khz, and the gain-bandwidth is 20khz. the total loop crossover frequency is chosen to be 200khz, which is 1/6 th of the clock frequency. this sets the second modulator pole at 2.5 times the crossover frequency. therefore the gain of the error amplifer can be 200khz/20khz = 10 at the frst modulator pole of 4khz. the error amp transconductance is 1ma/v , so this sets the r z resistor value in the com - pensation network at 10/1ma/v = 10k?. the zero frequency is placed at the frst pole to provide at total system response of -20db/decade (the zero from the error amp cancels the frst modulator pole, leaving the l1v al 2u 3u 4u 5u 6u 7u 8u 9u 10u mod_pole1 mod_pole2 gbw_modfb 0 4k 8k 12k 16k 20k 1 0 0.4m 0.8m 1.2m 1.6m 2.0m 2 0 10k 20k 30k 40k 50k 3 >> 1 2 3 conditions: v in =5v, v out =3.3v, f clk =1.4mhz, c out =10f, and mc v =132mv/s. the inductor is varied from 2h to 10h linearized modulator frequency response vs. inductor d etailed description
7 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation 1 pole rolloff from the error amp pole). the compensation capacitor becomes: cc = = (2 ? rz ? pole1) (6.28 ? 10k? ? 4khz) = 4nf soft start soft-start is accomplished by disconnect - ing the error amp and inserting a constant 2a current to charge the compensation capacitor. when power is frst applied and the reference establishes, the clamp circuit at the comp node sets its voltage at one vbe, which is the bottom of the inductor current range. the soft-start current continues to charge up the comp node, slowly raising the inductor cur - rent level. the inductor current will increase at approximately: (i refss / c c )? r pmos where: i refss = soft start constant current = 2a nominally c c = compensation capacitor r pmos = charging pmos resistance for typical circuit values of c c =6.8nf and r z =8k, the soft start period is tbd ms. the inductor current will eventually rise above the required load current and the out - put voltage will charge up. during soft-start the error amp is disconnected and acts as a comparator. when v( fb ) rises above the reference, the error amp switches to logic high and ends soft-start, at which point the error amp output is connected to the capaci - tated comp node. d etailed description the switching frequency will be reduced to half the normal frequency as long as v( fb ) is below 0.3v, as previously discussed in the over current protection section. 100% duty cycle in dropout to extend the battery life in portable applica - tions, the pwm control logic is set up such that if the output sr latch has not been reset by the current loop comparator at the end of a clock cycle, the charge signal continues to stay high into the beginning of the next cycle. this will happen naturally when the converter starts to go into dropout. the slope compensation ramp is reset every cycle. external clock synchronization the sp6652 has an internal 1.4mhz clock that can be defeated by connecting an ex - ternal clock pulse on the sync. the capture range for clock synchronization is 1.0 to 2.0mhz. when a clock pulse is present on the sync pin, the internal oscillator bias current is scaled back, handing control of the clock pulses to the faster external clock. the pulse width of the clock is approximately 50 ns, whether internally generated or ex - ternally applied. thermal shutdown the internal die temperature is monitored by a comparator that issues a too hot sig - nal when the junction temperature reaches 140?c, nominally. this signal that inhibits all internal circuits until the temperature has decreased to approximately 135?c, at which point a normal soft start sequence is initiated.
8 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation applications information vout c3 10 f r fb h r fb l syn c sd cc 10nf rz 4k ? 4.7 h l1 r1 10 ? c2 1 f c1 10 f vi n sp6652 1 2 3 4 5 10 9 8 7 6 pgnd sgnd fb comp sd lx pvin svin sync mode v in complete application circuit. the sp6652 pwm buck regulator circuit requires 3 capacitors: 10f for the p vin input, 1f input bypass for the s vin and 10f for the output are typically recommended. for the input capacitor, a value even larger than 10f will help reduce input voltage ripple for applications sensitive to ripple on the battery voltage. see the typical per - formance characteristics section for wave - forms on input and output ripple with 10f capacitors. all the capacitors should be surface mount ceramic for low lead induc - tance necessary at the 1.4mhz switching frequency of the sp6652 and to obtain low esr. this also helps improve bypassing on the input pin and ripple on the output. ceramic capacitors with x5r or x7r tem - perature grade are recommended for most applications. a selection of recommended capacitors is included in table 1. the 1f s vin input capacitor should have a series resistor of about 10 value connected from the input to the s vin pin to form an rc low pass flter to remove high frequency spikes present on the input switching pin component selection p vin . this will keep the sp6652 internal reference and other sensitive circuits noise free and ensure better output regulation. the gnd returns for the p vin capacitor and the output capacitor should be connected directly to the p gnd pin, which should con - nect to the thermal pad ground located un - der the sp6652. the gnd return for the 1f s vin capacitor should be connected to the s gnd pin, which should be connected separately to the p gnd pin to avoid adding p gnd noise to the sp6652 s gnd pin. see the typical sp6652 circuit layout for de - tails on the recommended layout. output voltage selection t o set the output voltage for the sp6652, a pair of resistors, r f and r i are used as a voltage divider between the output voltage at the output capacitor and the fb pin and gnd, as shown in the typical application cir - cuit. the recommended value for the r i re - sistor is 100k to 200k to keep the quies - cent current low, but not have the impedance too high at the fb pin for good regulation.
9 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation applications information manufacturers/ website part number inductance/ isat rating inductor length/width/thickness dcr max ohms coilcraft/ www.coilcraft mss5131-332mx 3.3uh/1.6a 5.1x5.1x3.1mm 0.032 coilcraft/ www.coilcraft mss5131-332mx 4.7uh/1.4a 5.1x5.1x3.1mm 0.045 sumida/ www.sumida.com cdrh3d28-3r3 3.3uh/2.0a 4.0x4.0x3.0mm 0.058 sumida/ www.sumida.com cdrh3d28-4r7 4.7uh/1.65a 4.0x4.0x3.0mm 0.071 wurth elektronik/ www.we-online.de we-tpc #744042003 3.3uh/1.8a 4.8/4.8/1.8mm 0.065 wurth elektronik/ www.we-online.de we-tpc #744042004 4.7uh/1.65a 4.8/4.8/1.8mm 0.082 table 2. inductor selection the range of typical inductor values and sizes are shown here in table 2. the output voltage can be set using the formula: v out = v fb *( + r f /r i ) where v fb = 0.8v typically, and for no-load t on is kept within 200nsec minimum: t on ( min ) = v out /(v in *freq). compensation component selection for simplicity in compensation with ce - ramic output capacitors, the sp6652 uses current mode pwm control, so all that is needed for stability is a series r z and c c at the comp pin to compensate the error amplifer. to see the actual sp6652 re - sponse with frequency, in fgure 3 we have taken a bode plot of gain and frequency re - sponse of the sp6652 circuit with 3.3vout. looking frst at the sp6652 modulator gain at low frequency you see a constant gain of about 26db and the frst pole or -3db point at about 4 khz, where the slope of the gain curve becomes about -20db/de - cade. at high frequency on the sp6652 modulator gain curve one can see the modulator curve slope increase down - ward for a high frequency pole at about 150khz, which is widely separated in frequency from the low frequency 4khz pole, so that the sp6652 can be compen - sated by a zero at the low frequency pole where the gain slope is only -20db/decade. the gain for the error amplifer is the cross - figure 3. sp6652 gain and frequency response 3.3v output voltage manufacturers/ website part number capacitance/ voltage capacitor size/type/thickness esr at 100khz tdk/www.tdk.com c1005x5r0j105m 1uf/6.3v 0402/x5r/0.5mm 0.03 tdk/www.tdk.com c1608x5r0j475k 4.7uf/6.3v 0603/x5r/0.9mm 0.02 tdk/www.tdk.com c2012x5r0j106m 10uf/6.3v 0805/x5r/1.35mm 0.02 murata/www.murata.com grm155r60j105ke19b 1uf/6.3v 0402/x5r/0.55mm 0.03 murata/www.murata.com grm188r60j475ke19 4.7uf/6.3v 0603/x5r/0.9mm 0.02 murata/www.murata.com grm21br60j106ke19l 10uf/6.3v 0805/x5r/1.35mm 0.02 table 1. capacitor selection note: component highlighted in bold is used on the sp6652eb evaluat ion board. note: component highlighted in bold is used on the sp6652eb evaluatio n board. sp6652 bode plot . -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 100 1000 10000 100000 1000000 log frequency -180 -150 -120 -90 -60 -30 0 30 60 90 120 150 180 sp6652 loop gain sp6652 modulator gain sp6652 loop phase sp6652 modulator phase pole1 -3db at 4khz a t 0db loop gain fo = 80khz loop phase = 50deg 3.3v out rz = 4k ? cc = 10nf -20db/dec (hz)
0 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation applications information figure 4. typical sp6652 circuit layout. over frequency f zero = 80khz (from the bode plot) divided by the loop gain band - width, given as 20khz, which is used in the following equation: error amp gain = f zero / ( loop gain bandwidth) = 80khz / 20khz = 4 the error amp transconductance is about 1ms, so this sets the r z resistor to be: rz = 4/1ms = 4k we will use r z = 4k for the 3.3v output compensation. the zero for loop compensation is placed at the frst modulator pole of 4 khz to pro - vide a loop response of -20/db/decade at the crossover frequency. the compensa - tion capacitor cc can be calculated from the crossover frequency pole1 and the r z value: c c = 1/(2 ? r z ? pole1) = 1/(2 ? 4k ? 4khz) = 10nf from the typical performance charac - teristics load step curves, the 2.5v output and 3.3v output are stable with r z = 4k and c c = 10nf. for 1.8v to 0.85v output, the values r z = 2k and c c = 10nf are recommended.
may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation typical performance characteristics sp6652 line/load rejection v out = 3.3v 3.20 3.25 3.30 3.35 3.40 0 200 400 600 800 1000 iload (ma) vi =3.6v vi =3.9v vi =4.2v vi =5.0v s p 6 6 5 2 l i n e / l o a d r e j e c t i o n v o u t = 1 . 5 v 1 . 4 8 0 1 . 4 9 0 1 . 5 0 0 1 . 5 1 0 1 . 5 2 0 1 1 0 1 0 0 1 0 0 0 i l o a d ( m a ) v o u t ( v ) . ( v v i = 4 . 2 v v i = 3 . 9 v v i = 3 . 6 v v i = 3 . 0 v figure 5. effciency vs. load, vout= 3.3v figure 6. effciency vs. load, vout= 1.5v figure 7: line/load rejection , vout = 3.3v figure 8: line/load rejection , vout = 1.5v sp6652 efficiency vs load v out = 3.3v 0 10 20 30 40 50 60 70 80 90 100 1 1 0 100 1000 iload (ma) vi =3.6v vi =3.9v vi =4.2v vi =5.0v s p 6 6 5 2 e f f i c i e n c y v s l o a d ( v o u t = 1 . 5 v ) 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 0 0 1 0 0 0 i l o a d ( m a ) e f f i c i e n c y ( % ) . ( v i = 3 . 0 v v i = 3 . 6 v v i = 3 . 9 v v i = 4 . 2 v sp6652 line/load regulation, v out = 3.3v 3.280 3.290 3.300 3.310 3.320 3.330 3.340 1 1 0 100 1000 iload (ma) vi =3.6v vi =3.9v vi =4.2v vi =5.0v figure 10: line/load regulation , log scale, vout = 1.5v figure 9: line/load regulation , log scale, vout = 3.3v s p 6 6 5 2 l i n e / l o a d r e j e c t i o n v o u t = 1 . 5 v 1 . 4 8 0 1 . 4 9 0 1 . 5 0 0 1 . 5 1 0 1 . 5 2 0 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 i l o a d ( m a ) v o u t ( v ) . ( v v i = 4 . 2 v v i = 3 . 9 v v i = 3 . 6 v v i = 3 . 0 v
may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation typical performance characteristics vo (ac) 200mv/div il1 (0.5a/div) iout (1.0a/div) vo (ac) 200mv/div il1 (0.5a/div) iout (0.5a/div) figure 11. 0ma to 600ma load step data vin=4.2v, vo=3.3v rz=4k , cz=10nf, l1=4.7uh figure 12. 0ma to 600ma load step data vin=4.2v, vo=1.5v rz=2k , cz=10nf, l1=4.7uh figure 13. 0ma to 600ma load step data vin=4.2v, vo=2.5v rz=4k , cz=10nf, l1=4.7uh
13 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation typical performance characteristics vo ut ilx 0.5a/div en vo ut ilx 0.5a/div en figure 15. sp6652 600ma start-up from enable vin=4.2v, vo=1.5v, iout = 600ma, rz=2k , cz=10nf, l1=4.7uh vi n (ac) vo ut (ac) vi n (a c) vo ut (a c) figure 17. sp6652 600ma input/output ripple vin=4.2v, vo=1.5v, iout = 600ma, rz=2k , cz=10nf, l1=4.7uh figure 16. sp6652 600ma input/output ripple vin=4.2v, vo=3.3v, iout = 600ma, rz=4k , cz=10nf, l1=4.7uh figure 14. sp6652 600ma start-up from enable vin=4.2v, vo=3.3v, iout = 600ma, rz=4k , cz=10nf, l1=4.7uh
4 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation package: 10 pin msop
5 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation package: 3x3 10 pin dfn
6 may25-07 revh sp6652 1a, high effciency, current mode pwm buck regulator ? 2007 sipex corporation ordering information part number msl level rohs min temp max temp package pack type quantity sp6652er-l l1 @ 260oc yes -40 85 dfn10 canister any sp6652er-l/tr l1 @ 260oc yes 0 70 dfn10 tape & reel 3000 sp6652eu-l/tr l1 @ 260oc yes 0 70 msop10 tape & reel 2500 sp6652eu-l l1 @ 260oc yes 0 70 msop10 tube 50 sp6652er l1 @ 240oc no -40 85 dfn10 canister any sp6652er/tr l1 @ 240oc no -40 85 dfn10 tape & reel 3000 sp6652eu l1 @ 240oc no 0 70 msop10 tube 50 sp6652eu-es l1 @ 240oc no 0 70 msop10 tube 50 sp6652eu/tr l1 @ 240oc no 0 70 msop10 tape & reel 2500 evaluation boards sp6652eb not applicable to board no 0 70 board not available in bulk sp6652ledeb not applicable to board no 0 70 board not available in bulk note: the sp6652eb is for regular sp6652 users, the s p652ledeb is for led driver users. for latest information on ordering status, go to the sip ex web landing page for this product http://www.sipex.com/productdetails.aspx?part=sp6652&k eyword=sp6652 solved by tm for further assistance: email: sipexsupport@sipex.com www support page: http://www.sipex.com/content.aspx?p=support sipex application notes: http://www.sipex.com/applicationnotes.aspx sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 sipex corporation reserves the right to make changes t o any products described herein. sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others.

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